1. Field of the Invention
The present invention relates to a digital level shift circuit, and more particularly to an improved CMOS (Complementary Metal Oxide Semiconductor) digital level shift circuit capable of outputting a high level voltage using transistors having a low level channel breakdown voltage.
2. Description of the Background Art
FIG. 1 illustrates a conventional CMOS digital level shift circuit. As shown therein, an inverter 1 outputs a first source voltage Vcc in accordance with a logic state of an input signal Vin. The inverter 1 includes a PMOS transistor P1 and an NMOS transistor N1. The PMOS transistor P1 includes a source connected to the first source voltage Vcc, a gate connected the gate of NMOS transistor N1 for receiving the input signal Vin, and a drain connected the drain of NMOS transistor N1 through an output terminal OUT1. The source of the NMOS transistor N1 is connected to the ground voltage Vss.
A latch circuit 2 outputs a second source voltage Vdd in accordance with a logic state of the input signal Vin. The latch circuit 2 includes a pair of PMOS transistors P21, P22 with their sources connected the second source voltage Vdd. and a pair of NMOS transistors N21, N22 with their drains connected to the drains of the PMOS transistors P21, P22, respectively, and their sources connected the ground voltage Vss.
The gate of the NMOS transistor N21 is connected with the output terminal OUT1 of the inverter 1, the gate of the PMOS transistor P22 is connected to the drains of the PMOS and NMOS transistors P21, N21, and the gate of the PMOS transistor P21 is connected to an output terminal OUT2 and to the drains of the PMOS and NMOS transistors P22, N21.
Here, the level of the second source voltage Vdd is higher than that of the first source voltage Vcc.
The operation of the above-described conventional CMOS digital level shift circuit will now be described.
When the input signal Vin is in a low level, the PMOS transistor P1 in the inverter 1 is turned on and the NMOS transistor N1 is turned off, whereby the first source voltage Vcc is output to the output terminal OUT1. The NMOS transistor N21 in the latch circuit 2 is turned on by the first source voltage Vcc and the drain of the NMOS transistor N21 at node NO1 has the ground voltage level. At the same time, since the gate of the PMOS transistor P22 is connected to the node NO1, the transistor P22 is turned on so that the node NO2 has the voltage level of the second source voltage Vdd. The level of the second source voltage Vdd is output at the output terminal OUT2 of the latch circuit 2. The NMOS transistor N22 also receives the low level input signal Vin through its gate and is turned off.
When the input signal Vin is in a high level, the PMOS transistor P1 in the inverter 1 is turned off and the NMOS transistor N1 is turned on, whereby the ground voltage is output at the output terminal OUT1. This turns off the NMOS transistor N21 in the latch circuit 2. However, the NMOS transistor N22 is turned on as the high level input signal Vin is applied to its gate, whereby the ground voltage is output at the output terminal OUT2.
When the node NO2 is in the ground voltage level, the PMOS transistor P21 is turned on, so that the node NO1 obtains the second source voltage Vdd level. This turns off the PMOS transistor P22.
The conventional CMOS digital level shift circuit employs the first source voltage Vcc and the second source voltage Vdd having a higher voltage level than Vcc, so as to externally output the higher second source voltage Vdd to an external circuit (not shown) connected thereto.
In order for the conventional circuit function properly, however, the channel breakdown voltages of the two transistors N1, P1 in the inverter 1 need to be greater than the first source voltage Vcc, and the channel breakdown voltages of the four transistors N21, N22, P21, P22 in the latch circuit 2 need to be greater than the second source voltage Vdd. The level of the second source voltage Vdd which is output through the output terminal OUT2 of the latch circuit 2 should be confined below the channel breakdown voltage levels of the four transistors N21, N22, P21, P22 in the latch circuit 2. Otherwise, the transistors N21, N22, P21, P22 will rupture due to insulation.
Therefore, the conventional CMOS digital level shift circuit has a disadvantage in that it requires use of a transistor with a high channel breakdown voltage if a high level source voltage were to be output.